1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
The degree of integration of semiconductor integrated circuits, namely, integrated circuits using metal oxide semiconductor (MOS) transistors, has been increasing. The increasing degree of integration of such integrated circuits results in MOS transistors having small sizes reaching nano-scale dimensions. Inverter circuits are fundamental circuits of digital circuits, and the increasing decrease in the size of MOS transistors included in inverter circuits causes difficulty in suppressing leak currents, leading to problems of reduced reliability due to hot carrier effects and of the reduction in the area of the circuits being prevented because of the requirements of the secure retention of necessary currents. To overcome the above problems, a surrounding gate transistor (SGT) having a structure in which a source, gate, and drain are arranged vertically with respect to a substrate and in which the gate surrounds an island-shaped semiconductor layer has been proposed (for example, Japanese Unexamined Patent Application Publications No. 2-71556, No. 2-188966, and No. 3-145761).
It is known that in a static memory cell, the current driving force of a driver transistor is made double the current driving force of an access transistor to ensure operational stability (H. Kawasaki, M. Khater, M. Guillorn, N. Fuller, J. Chang, S. Kanakasabapathy, L. Chang, R. Muralidhar, K. Babich, Q. Yang, J. Ott, D. Klaus, E. Kratschmer, E. Sikorski, R. Miller, R. Viswanathan, Y. Zhang, J. Silverman, Q. Ouyang, A. Yagishita, M. Takayanagi, W. Haensch, and K. Ishimaru, “Demonstration of Highly Scaled FinFET SRA M Cells with High-κ/Metal Gate and Investigation of Characteristic Variability for the 32 nm node and beyond”, IEDM, pp. 237-240, 2008).
To construct a static memory cell using the above SGT, two driver transistors are used because of the need for a double gate width in order to make it feasible to make the current driving force of a driver transistor double the current driving force of an access transistor to ensure operational stability. This leads to an increase in memory cell area.
Further, an SGT production method has been proposed of forming a pillar-shaped semiconductor layer, depositing a gate conductive film on the pillar-shaped semiconductor layer, performing planarization, and then etching back the gate conductive film to obtain a desired length (Japanese Unexamined Patent Application Publication No. 2009-182317). This high-degree-of-integration, high-performance, and high-yield SGT production method allows the physical gate length of the SGT to be kept uniform over all the transistors on a wafer.
Additionally, the increasing decrease in the size of static memory cells reduces the gate capacitance or diffusion layer capacitance of a MOS transistor to be connected to a storage node because of the reduction in dimensions. In this case, if the static memory cell is irradiated with radiation from the outside, electron-hole pairs are generated in a semiconductor substrate along the path of radiation, and at least the electrons or holes of the electron-hole pairs flow into a diffusion layer that forms the drain, causing data inversion. Thus, a soft-error phenomenon occurs in that data cannot be correctly held. The soft-error phenomenon has become a serious problem in recent static memory cells whose sizes have been reduced because as the decrease in the size of memory cells increases, the reduction in the gate capacitance or diffusion layer capacitance of the MOS transistor to be connected to the storage node becomes more noticeable than the electron-hole pairs generated by radiation. Therefore, it has been reported that a capacitor is formed in a storage node of a static memory cell to ensure sufficient electrical charges in the storage node so that the occurrence of soft errors can be avoided to ensure operational stability (Japanese Unexamined Patent Application Publication No. 2008-227344).